In a typical manufacturing process of a semiconductor integrated circuit, defective products are included in produced products in a constant rate, so that the defective products are removed through a test process, and only good products are delivered rate of the good products at this time is referred to as a “yield”. If the yield is low, a manufacturing cost increases to put pressure on profits. For this reason, it is necessary to clarify a cause of a failure by failure analysis to improve the manufacturing process, and thereby improve the yield (for example, Japanese Patent Publication (JP 2006-133122A; patent literature 1).
The patent literature 1 discloses a technique that can deal with reduction of an amplitude voltage and an element size, and facilitate measurement of a voltage waveform by a laser voltage probe. In the technique of the patent literature 1, an observation target region for the voltage waveform and an LVP measuring element are connected to each other to perform LVP measurement with the LVP measuring element as a laser irradiation position, and thereby the voltage waveform is measured. At this time, a drain diffusion region and a source diffusion region of the LVP measuring element having a MOS capacitance structure are applied with the voltage waveform of the observation region by metal interconnections. Also, a gate is applied with a voltage waveform of reverse logic to that of the observation region. Thus, a bandgap of a channel surface of the LVP measuring element can vary along with a logic transition of the observation region, and thereby a situation in which the Franz-Keldysh effect appears to change an optical absorbance is observed by the LVP measurement.
However, as an integration degree of a circuit is increased, failure analysis of the circuit becomes difficult. For example, voltage waveform measurement by an electron beam system (EB measurement) is difficult because, in a current situation in which the number of interconnection layers increases to around eight, the interconnection layer to be measured is not often exposed. Also, a laser voltage probe measurement method (hereinafter, to be referred to as an LVP (Laser Voltage Probe)) is a method that measures a voltage waveform by laser irradiation from a back surface of a chip, and usable even in the case of a large number of interconnection layers. However, due to a lack of resolution, it is impossible to measure all transistors in the 90 nm generation or the subsequent.
Also, as a method of measuring a voltage waveform inside an integrated circuit, the following method is considered. That is, an interconnection exposure process is performed by an FIB (Focused Ion Beam) apparatus, and then the EB measurement is performed. However, this method requires quite a lot of work time. For this reason, first, it is necessary to roughly estimate a failure position with failure diagnostic software, and then to specify the failure position through measurement on the basis of a result of the estimation. It should be noted that the failure diagnostic software is software that “estimates” the failure position on the basis of a circuit diagram of the integrated circuit and a test result. Also, the failure position extracted from the estimation is referred to as a “failure candidate”.
It should be noted that the number of “failure candidates” estimated by the above failure diagnostic software may be very large depending on a structure of a desired circuit. A measurement is required to check which of the failure candidates is a true failure, and in the measurement, the interconnection exposure process by the FIB system is performed as described above. For this reason, as the number of failure candidates increases, a measurement time becomes longer, and therefore a work time required for failure analysis is increased.
Non-patent literature 1 describes an observation point selecting method intended to improve easiness of failure analysis in a few observation points. According to the method, by referring to gate level circuit connection data (netlist), observation points are first inserted into all nodes inside a circuit. Then, the number of failures (equivalent failures) Np that cannot be specified by external observation is calculated. At this time, all the nodes in the circuit can be observed, and therefore Np is 0. Subsequently, observation points are removed from nodes such that Np is not increased and removal of the observation points causes only a small increase in Np, even if observation points are removed. That is, the observation points are removed with the increase in Np being suppressed minimally. Thus, it is expected that the easiness of failure analysis is improved with a small number of observation points.
According to Non-patent literature 1, when the insertion positions of the observation points are determined, only the circuit netlist is used, but a failure generation probability at each of the nodes is not taken into account. For this reason, the observation points may be uselessly inserted into nodes at which the failure generation probability is low. There is known a technique on a circuit design system that can efficiently facilitate failure analysis with fewer observation points (for example, patent literature 2).
The patent literature 2 discloses a circuit design system provided with a storage section 103, a failure candidate extracting section 109, a determining section 111, and an observation point insertion section 113. FIG. 1 is a block diagram illustrating the configuration of the circuit design system disclosed in the patent literature 2.
Referring to FIG. 1, the storage section 103 stores a netlist NET. The failure candidate extracting section 109 extracts equivalent failure groups G1 to GI (I is an integer not less than 1) from the netlist NET, and generates failure candidate data CAN showing the equivalent failure group Gi (i is an integer not less than 1 and not more than I).
The equivalent failure group Gi includes a plurality of nodes Ni1 to NiJi (Ji means the number of nodes included in the equivalent failure group Gi). The determining section 111 determines a target node into which an observation point used for failure analysis is inserted, from the plurality of nodes Ni1 to Niji. In this process, the determining section 111 determines the target node based on the number of nodes Ji. The observation point insertion section 113 inserts one or more observation points into the target node to update the netlist NET.
In the conventional circuit design system, the determining section determines the target node into which the at least one observation point used for failure analysis is inserted, from the plurality of nodes Ni1 to NiJi. The observation point insertion section inserts the at least one observation point into the target node to thereby update the netlist. FIG. 2 is a layout diagram illustrating a layout of a circuit designed by the circuit design system described in the patent literature 2. As illustrated in FIG. 2, in the circuit, elements (hereinafter may be described as LVP_PADs) that are analyzable by the laser voltage probe measurement method are newly additionally inserted. However, if an observation point is inserted into a critical path (maximum delay path), an operation speed of the entire circuit may be reduced because of an increase in delay. If this causes a problem, the LVP_PAD is selectively inserted into a position not corresponding to the critical path (maximum delay path) in the conventional technique.